Read e-book online 6502 Applications Book PDF

By Rodnay Zaks

ISBN-10: 0895880156

ISBN-13: 9780895880154

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Once the "data ready" signal has been recognized, data can be read from the ORA and transferred to their final memory location, which we will assume to be, as usual, memory location 20: LDA STA ORA $20 Reading the contents of ORA into the accumulator will also automatically clear bit I of IFR (the CAI status indicator), so that the internal interrupt will be automatically reset. It is important to remember that interrupt flags must explicitly be cleared every time they are used. The 6522 is organized in such a way that the "normal" operation, such as reading the contents of ORA after detecting an interrupt, will take care of it automatically.

A Handshake Protocol on Input We will assume here that the complete handshake sequence is used: first the program is responsible for sending a "start" pulse (active high) to the device. Later, the device will respond with a "data ready" strobe (active high-to-low here), and the program will be responsible for determining that the signal has been received, then transferring the data into memory location 20. The program appears below: NS HAKE WAIT LOA STA STA LOA STA LOA STA LOA STA LOA AND BEQ LOA STA #0 DORA ACR #$0C PCR #$OE PCR #$0C PCR IFR #$02 WAIT ORA $20 A IS INPUT BITS 2 AND 3 ON CLEAR START PULSE BITS l, 2, 3 ON GENERATE START ON CA2 CLEAR IT INTERRUPT?

Four sets of registers can be distinguished as to their function: 1. 2. 3. 4. The PIO registers (addresses Othrough 3, plus address F). The timer registers (two timers, addresses 4 through 9. The shift register (address A). The control registers (addresses B through E). These four sets will now be examined in detail to explain the capabilities of the 6522. 31 6502 APPLICATIONS BOOK 00 ORB (PBO TO PB7) 1/0 data, part A 01 ORA (PAO TO PA7) used far control-affects handshake 02 DDR B 03 DOR A 04 Tl L-L/Tl C-L counter-low 05 TlC-H counter-high 06 Tl L-L latch-law 07 Tll-H latch-high 08 T2L-LIT2C-L 09 T2C-H OA SR OB ACR data direction registers ( timer] latch-low counter-low I ,Omo,2 oc counter-high shift register auxiliary peripheral PCR (CA1,CA2,CB2,CB1) IFR flags OE IER enable OF ORA OD } function control } interrupt control output register A (does not affect handshake) Fig.

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6502 Applications Book by Rodnay Zaks

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